| 8:00AM-8:45AM |
Breakfast/registration
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|
| 8:45AM-9:45AM |
Session: FPGA
Chair: Thierry Tambe |
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Secure Computing SoC for Physical AI, Data Center, and Mission Critical Systems
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Jaideep Dastidar & Thomas To, AMD |
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Versal RF
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Jeff Cuppett, AMD |
| 9:45AM-10:45AM |
Session: Memory
Chair: Jae W. Lee |
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Samsung LPDDR5X-PIM: World’s First LPDDR based Processing in Memory (PIM) Solution for AI Inference
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Karam Hwang, Samsung |
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XCENA MX1 CXL Computational Memory Device
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Harry Kim (XCENA) & Jinin So (Samsung Electronics) |
| 10:45AM-11:15AM |
Break
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|
| 11:15AM-12:45PM |
Session: Networking & Interconnect
Chair: Greg Papadopoulos |
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Thor Ultra: An Ethernet NIC Chip Optimized for AI & HPC
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Hemal Shah, Broadcom |
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NVIDIA BlueField-4 Processor Powers the AI Factory Operating System
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Idan Burstein, NVIDIA |
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NVIDIA Spectrum-X Multiplane Network Architecture
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Gilad Shainer, NVIDIA |
| 12:45PM-2:15PM |
Lunch
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|
| 2:15PM-4:15PM |
Session: AI 1
Chair: Sherry Xu & John Wright |
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Meta’s Custom AI Silicon: From Recommendation to Dual-Mandate with GenAI
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Srinagesh Loke, Cindy Chen & Jatinder Singh, Meta |
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Think Fast: LPU Accelerator for Heterogeneous Compute
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Igor Arsovski & Santosh Raghavan, NVIDIA |
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The Cerebras Rack-Scale Architecture for Wafer Scale Engine
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Jean-Philippe (J.P.) Fricker, Cerebras |
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MAIA 200: A Data Center Scale AI system - MAIA-200 Accelerator
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Prashant Ranjan & Jackson Peng, Microsoft |
| 4:15PM-4:45PM |
Break
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|
| 4:45PM-6:15PM |
Session: AI 2
Chair: Brucek Khailany |
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Dataflow at Scale: the SN50 RDU
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Raghu Prabhakar, SambaNova |
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The Eighth Generation TPU Family: Two Chips Optimized for Training and Serving in the Agentic Era
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Norman Jouppi & Sridhar Lakshmanamurthy, Google |
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You Can Just Build Things … Chips
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Richard Ho, Ravi Narayanaswami & Chris Leary, OpenAI |
| 6:15PM-6:20PM |
Vice-Chair closing remarks
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Vice-Chair closing remarks
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Nhon Quach |